111 search results - page 18 / 23 » IPR: An Integrated Placement and Routing Algorithm |
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
Increasing power densities in Field Programmable Gate Arrays (FPGAs) have made them susceptible to thermal problems. The advent of platform FPGAs has further exacerbated the probl...
ISQED
2005
IEEE
15 years 5 months ago
2005
IEEE
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
86
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GLVLSI
2009
IEEE
15 years 6 months ago
2009
IEEE
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
113
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ISPD
2005
ACM
15 years 5 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
ISPD
2005
ACM
15 years 5 months ago
2005
ACM
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...