111 search results - page 20 / 23 » IPR: An Integrated Placement and Routing Algorithm |
ISPD
2005
ACM
15 years 5 months ago
2005
ACM
In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and the bus specification (the width of each bus and the blocks that the bus need to g...
102
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ISPD
2009
ACM
15 years 6 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
195
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DAC
2011
ACM
13 years 11 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
DAC
2010
ACM
15 years 21 days ago
2010
ACM
This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can...
DAC
2008
ACM
16 years 18 days ago
2008
ACM
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...