111 search results - page 5 / 23 » IPR: An Integrated Placement and Routing Algorithm |
ASPDAC
1998
ACM
15 years 3 months ago
1998
ACM
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...
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ISPD
2012
ACM
13 years 7 months ago
2012
ACM
We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
ISPD
2010
ACM
15 years 6 months ago
2010
ACM
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
DAC
2006
ACM
16 years 17 days ago
2006
ACM
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...