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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
15 years 6 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
CVPR
2010
IEEE
15 years 6 months ago
Improving State-of-the-Art OCR through High-Precision Document-Specific Modeling
Optical character recognition (OCR) remains a difficult problem for noisy documents or documents not scanned at high resolution. Many current approaches rely on stored font models...
Andrew Kae, Gary Huang, Erik Learned-miller, Carl ...
IEEEARES
2010
IEEE
15 years 4 months ago
FedWare: Middleware Services to Cope with Information Consistency in Federated Identity Management
—Collaborations by the use of inter-organizational business processes can help companies to achieve a competitive edge over competing businesses. Typically, these collaborations ...
Thorsten Höllrigl, Jochen Dinger, Hannes Hart...
IUI
2010
ACM
15 years 4 months ago
DocuBrowse: faceted searching, browsing, and recommendations in an enterprise context
Browsing and searching for documents in large, online enterprise document repositories are common activities. While internet search produces satisfying results for most user queri...
Andreas Girgensohn, Frank M. Shipman III, Francine...
PAM
2010
Springer
15 years 4 months ago
Toward Topology Dualism: Improving the Accuracy of AS Annotations for Routers
Abstract. To describe, analyze, and model the topological and structural characteristics of the Internet, researchers use Internet maps constructed at the router or autonomous syst...
Bradley Huffaker, Amogh Dhamdhere, Marina Fomenkov...