25 search results - page 3 / 5 » Identifying and Exploiting Spatial Regularity in Data Memory... |
SIGMETRICS
1992
ACM
15 years 2 months ago
1992
ACM
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
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ICS
1995
Tsinghua U.
15 years 1 months ago
1995
Tsinghua U.
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
MICRO
1997
IEEE
15 years 2 months ago
1997
IEEE
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
IEEEPACT
1999
IEEE
15 years 2 months ago
1999
IEEE
The performance of applications on large shared-memory multiprocessors with coherent caches depends on the interaction between the granularity of data sharing, the size of the coh...
CC
2003
Springer
15 years 3 months ago
2003
Springer
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...