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IPPS
2006
IEEE
15 years 11 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
148
Voted
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
15 years 11 months ago
A 52mW 1200MIPS compact DSP for multi-core media SoC
- This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-c...
Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting ...
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
15 years 10 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...
142
Voted
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
15 years 10 months ago
Reconfigurable SoC - What Will it Look Like?
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chri...
ISSS
2002
IEEE
130views Hardware» more  ISSS 2002»
15 years 10 months ago
System-Level Modeling of a Network Switch SoC
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...
Andrew S. Cassidy, Christopher P. Andrews, Donald ...