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ASAP
2006
IEEE
169views Hardware» more  ASAP 2006»
14 years 13 days ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben...
SIGGRAPH
1993
ACM
13 years 10 months ago
View interpolation for image synthesis
Image-space simplifications have been used to accelerate the calculation of computer graphic images since the dawn of visual simulation. Texture mapping has been used to provide a...
Shenchang Eric Chen, Lance Williams
ICSE
2008
IEEE-ACM
14 years 7 months ago
Design and implementation of the software architecture for a 3-D reconstruction system in medical imaging
The design and implementation of the reconstruction system in medical X-ray imaging is a challenging issue due to its immense computational demands. In order to ensure an efficien...
Holger Scherl, Stefan Hoppe, Markus Kowarschik, Jo...
SASP
2009
IEEE
238views Hardware» more  SASP 2009»
14 years 1 months ago
Hardware acceleration of multi-view face detection
—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotat...
Junguk Cho, Bridget Benson, Ryan Kastner
ICANN
2010
Springer
13 years 7 months ago
Accelerating Large-Scale Convolutional Neural Networks with Parallel Graphics Multiprocessors
Training convolutional neural networks (CNNs) on large sets of high-resolution images is too computationally intense to be performed on commodity CPUs. Such architectures however ...
Dominik Scherer, Hannes Schulz, Sven Behnke