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» Impact Analysis of Process Variability on Clock Skew
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DATE
2003
IEEE
116views Hardware» more  DATE 2003»
15 years 2 months ago
Statistical Timing Analysis Using Bounds
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sar...
84
Voted
ICMLA
2009
14 years 7 months ago
Sensitivity Analysis of POMDP Value Functions
In sequential decision making under uncertainty, as in many other modeling endeavors, researchers observe a dynamical system and collect data measuring its behavior over time. The...
Stéphane Ross, Masoumeh T. Izadi, Mark Merc...
ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
15 years 4 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram
TCAD
2008
93views more  TCAD 2008»
14 years 9 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
DAC
2004
ACM
15 years 1 months ago
Statistical gate delay model considering multiple input switching
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
Aseem Agarwal, Florentin Dartu, David Blaauw