2 search results - page 1 / 1 » Impact of Gate-Length Biasing on Threshold-Voltage Selection |
93
Voted
ISQED
2006
IEEE
15 years 7 months ago
2006
IEEE
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
109
Voted
ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...