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» Impact of Technology Scaling in the Clock System Power
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CSE
2009
IEEE
15 years 26 days ago
Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC
— Low energy consumption is a critical issue in embedded systems design. As the technology feature sizes of SoC (Systems on Chip) become smaller and smaller, the percentage of le...
Meikang Qiu, Laurence Tianruo Yang, Edwin Hsing-Me...
DAC
2001
ACM
15 years 10 months ago
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
Jafar Savoj, Behzad Razavi
ICCD
2004
IEEE
113views Hardware» more  ICCD 2004»
15 years 6 months ago
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
Radu Marculescu, Diana Marculescu, Larry T. Pilegg...
SC
2009
ACM
15 years 4 months ago
Future scaling of processor-memory interfaces
Continuous evolution in process technology brings energyefficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high ba...
Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis,...
CSCW
2008
ACM
14 years 11 months ago
The view from the trenches: organization, power, and technology at two nonprofit homeless outreach centers
Nonprofit social service organizations provide the backbone of social support infrastructure in the U.S. and around the world. As the ecology of information exchange moves evermor...
Christopher A. Le Dantec, W. Keith Edwards