419 search results - page 13 / 84 » Impact of Technology Scaling in the Clock System Power |
120
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TVLSI
2010
14 years 4 months ago
2010
With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fail...
89
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DSD
2002
IEEE
15 years 2 months ago
2002
IEEE
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
128
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ICCD
2008
IEEE
15 years 6 months ago
2008
IEEE
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance op...
ISPASS
2005
IEEE
15 years 3 months ago
2005
IEEE
We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use— instrument...