419 search results - page 16 / 84 » Impact of Technology Scaling in the Clock System Power |
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USENIX
2008
14 years 12 months ago
2008
This paper describes Mortar, a distributed stream processing platform for building very large queries across federated systems (enterprises, grids, datacenters, testbeds). Nodes i...
ICCD
2003
IEEE
15 years 6 months ago
2003
IEEE
High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technol...
DT
2006
14 years 9 months ago
2006
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
ECCTD
2011
13 years 9 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...