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» Impact of Technology Scaling in the Clock System Power
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CF
2010
ACM
15 years 1 months ago
Towards greener data centers with storage class memory: minimizing idle power waste through coarse-grain management in fine-grai
Studies have shown much of today’s data centers are over-provisioned and underutilized. Over-provisioning cannot be avoided as these centers must anticipate peak load with burst...
In Hwan Doh, Young Jin Kim, Jung Soo Park, Eunsam ...
ISPD
2004
ACM
134views Hardware» more  ISPD 2004»
15 years 3 months ago
Performance-driven register insertion in placement
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
Dennis K. Y. Tong, Evangeline F. Y. Young
ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
15 years 4 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...
DSN
2002
IEEE
15 years 2 months ago
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
IPPS
2005
IEEE
15 years 3 months ago
Improvement of Power-Performance Efficiency for High-End Computing
Left unchecked, the fundamental drive to increase peak performance using tens of thousands of power hungry components will lead to intolerable operating costs and failure rates. R...
Rong Ge, Xizhou Feng, Kirk W. Cameron