419 search results - page 21 / 84 » Impact of Technology Scaling in the Clock System Power |
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
Any architectural optimization aims at satisfying the end user. However, modern architectures execute with little to no knowledge about the individual user. If architectures could...
ASYNC
2000
IEEE
15 years 2 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
123
Voted
PLDI
2003
ACM
15 years 2 months ago
2003
ACM
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
SIGMETRICS
2010
ACM
15 years 2 months ago
2010
ACM
Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based o...