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» Impact of Technology Scaling in the Clock System Power
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WEBI
2005
Springer
15 years 3 months ago
Multi-Faceted Information Retrieval System for Large Scale Email Archives
We profile a system for search and analysis of largescale email archives. The system builds around four facets: Content-based search engine, statistical topic model, automaticall...
Jukka Perkiö, Ville H. Tuulos, Wray L. Buntin...
AINA
2007
IEEE
15 years 4 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
SAMOS
2007
Springer
15 years 3 months ago
Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors
When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however...
Pepijn J. de Langen, Ben H. H. Juurlink
84
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ISLPED
2003
ACM
149views Hardware» more  ISLPED 2003»
15 years 2 months ago
Elements of low power design for integrated systems
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
Sung-Mo Kang
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
15 years 3 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy