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» Impact of Technology Scaling in the Clock System Power
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ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
15 years 4 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
64
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ISCAS
2005
IEEE
119views Hardware» more  ISCAS 2005»
15 years 3 months ago
Analysis of power consumption in VLSI global interconnects
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
Youngsoo Shin, Hyung-Ock Kim
DATE
2007
IEEE
156views Hardware» more  DATE 2007»
15 years 4 months ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
90
Voted
RTAS
2005
IEEE
15 years 3 months ago
Practical On-line DVS Scheduling for Fixed-Priority Real-Time Systems
We present an on-line Dynamic Voltage Scaling (DVS) algorithm for preemptive fixed-priority real-time systems called low power Limited Demand Analysis with Transition overhead (l...
Bren Mochocki, Xiaobo Sharon Hu, Gang Quan
LCPC
2004
Springer
15 years 3 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...