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» Impact of Technology Scaling in the Clock System Power
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IJHPCA
2008
75views more  IJHPCA 2008»
14 years 9 months ago
Towards Ultra-High Resolution Models of Climate and Weather
We present a speculative extrapolation of the performance aspects of an atmospheric general circulation model to ultra-high resolution and describe alternative technological paths...
Michael F. Wehner, Leonid Oliker, John Shalf
90
Voted
BMCBI
2006
126views more  BMCBI 2006»
14 years 9 months ago
Genomes as geography: using GIS technology to build interactive genome feature maps
Background: Many commonly used genome browsers display sequence annotations and related attributes as horizontal data tracks that can be toggled on and off according to user prefe...
Mary E. Dolan, Constance C. Holden, M. Kate Beard,...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
15 years 3 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DAC
2004
ACM
15 years 10 months ago
Design optimizations for microprocessors at low temperature
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with...
Arman Vassighi, Ali Keshavarzi, Siva Narendra, Ger...
59
Voted
DAC
2009
ACM
15 years 10 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...