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» Impact of Technology Scaling in the Clock System Power
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ISCC
2008
IEEE
152views Communications» more  ISCC 2008»
15 years 4 months ago
Efficient delivery of MBMS multicast traffic over HSDPA
Multimedia Broadcast/Multicast Service (MBMS) and High-Speed Downlink Packet Access (HSDPA) are two key technologies that constitute a significant step towards the Mobile Broadban...
Antonios G. Alexiou, Christos Bouras, Evangelos Re...
81
Voted
CASES
2008
ACM
14 years 11 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
WWW
2009
ACM
15 years 10 months ago
OpenRuleBench: an analysis of the performance of rule engines
The Semantic Web initiative has led to an upsurge of the interest in rules as a general and powerful way of processing, combining, and analyzing semantic information. Since severa...
Senlin Liang, Paul Fodor, Hui Wan, Michael Kifer
PPL
2008
185views more  PPL 2008»
14 years 9 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
15 years 4 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...