419 search results - page 62 / 84 » Impact of Technology Scaling in the Clock System Power |
LISA
2007
15 years 23 hour ago
2007
Network patterns are based on generic algorithms that execute on tree-based overlays. A set of such patterns has been developed at KTH to support distributed monitoring in network...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ISCAS
1999
IEEE
15 years 2 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
CASES
2008
ACM
14 years 11 months ago
2008
ACM
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
ARCS
2009
Springer
15 years 4 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...