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» Impact of Technology Scaling in the Clock System Power
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LCN
2008
IEEE
15 years 4 months ago
Real-time performance analysis of Adaptive Link Rate
—High speed links are widely deployed in modern day computer networks to meet the ever growing needs for increasing data bandwidth. However, with the increase in the link rate, t...
Baoke Zhang, Karthik Sabhanatarajan, Ann Gordon-Ro...
ISCA
2010
IEEE
170views Hardware» more  ISCA 2010»
15 years 2 months ago
Relax: an architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaral...
DSN
2005
IEEE
15 years 3 months ago
Reversible Fault-Tolerant Logic
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
P. Oscar Boykin, Vwani P. Roychowdhury
JUCS
2006
112views more  JUCS 2006»
14 years 9 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
ICCD
2008
IEEE
202views Hardware» more  ICCD 2008»
15 years 6 months ago
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
Andrea Pellegrini, Kypros Constantinides, Dan Zhan...