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ICCD
1994
IEEE
85views Hardware» more  ICCD 1994»
15 years 1 months ago
A Superassociative Tagged Cache Coherence Directory
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
David J. Lilja, Shanthi Ambalavanan
IPPS
2008
IEEE
15 years 4 months ago
A deterministic multi-way rendezvous library for haskell
The advent of multicore processors requires mainstream concurrent programming languages with high level concurrency constructs and effective debugging techniques. Unfortunately, m...
Nalini Vasudevan, Satnam Singh, Stephen A. Edwards
ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
15 years 3 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
TPHOL
2009
IEEE
15 years 4 months ago
A Formalisation of Smallfoot in HOL
In this paper a general framework for separation logic inside the HOL theorem prover is presented. This framework is based on Abeparation Logic. It contains a model of an abstract,...
Thomas Tuerk
RTAS
2009
IEEE
15 years 4 months ago
QeDB: A Quality-Aware Embedded Real-Time Database
QeDB is a database for data-intensive real-time applications running on flash memory-based embedded systems. Currently, databases for embedded systems are best effort, providing ...
Woochul Kang, Sang Hyuk Son, John A. Stankovic