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IJCNN
2006
IEEE
15 years 3 months ago
A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering
— We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the ...
Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K....
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
15 years 3 months ago
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs
This paper describes a fast-lock mixed-mode delaylocked loop (MMDLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time...
Kuo-Hsing Cheng, Yu-lung Lo
ESORICS
2002
Springer
15 years 9 months ago
Hamming Weight Attacks on Cryptographic Hardware - Breaking Masking Defense
It is believed that masking is an effective countermeasure against power analysis attacks: before a certain operation involving a key is performed in a cryptographic chip, the inpu...
Marcin Gomulkiewicz, Miroslaw Kutylowski
IJHPCA
2010
84views more  IJHPCA 2010»
14 years 8 months ago
Operation Stacking for Ensemble Computations With Variable Convergence
Sparse matrix operations achieve only small fractions of peak CPU speeds because of the use of specialized, indexbased matrix representations, which degrade cache utilization by i...
Mehmet Belgin, Godmar Back, Calvin J. Ribbens
RECONFIG
2009
IEEE
269views VLSI» more  RECONFIG 2009»
15 years 4 months ago
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
Guilherme Guindani, Frederico Ferlini, Jeferson Ol...