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    High-level synthesis for large bit-width multipliers on FPGAs: a case study
    13 years 12 months ago
    High-level synthesis for large bit-width multipliers on FPGAs: a case study
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    In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
    Gang Quan, James P. Davis, Siddhaveerasharan Devar...
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