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» Implementations of Grid-Based Distributed Parallel Computing
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IPPS
2006
IEEE
15 years 11 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
EUROPAR
2009
Springer
15 years 9 months ago
A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor
We consider a multi-processor system-on-chip destined for streaming applications. An application is composed of one input and one output queue and in-between, several levels of ide...
Daniela Genius, Alix Munier Kordon, Khouloud Zine ...
127
Voted
ICA3PP
2009
Springer
15 years 9 months ago
A Software Transactional Memory Service for Grids
In-memory data sharing for grids allow location-transparent access to data stored in volatile memory. Existing Grid middlewares typ- ically support only explicit data transfer betw...
Kim-Thomas Möller, Marc-Florian Müller, ...
ICDCS
2012
IEEE
13 years 7 months ago
Scaling Down Off-the-Shelf Data Compression: Backwards-Compatible Fine-Grain Mixing
—Pu and Singaravelu presented Fine-Grain Mixing, an adaptive compression system which aimed to maximize CPU and network utilization simultaneously by splitting a network stream i...
Michael Gray, Peter Peterson, Peter L. Reiher
136
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ICPP
2008
IEEE
15 years 11 months ago
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a f...
Sangyeun Cho, Socrates Demetriades, Shayne Evans, ...