3398 search results - page 643 / 680 » Implementations of Grid-Based Distributed Parallel Computing |
112
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HPCA
2011
IEEE
14 years 4 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
132
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HPCA
2012
IEEE
13 years 8 months ago
2012
IEEE
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
130
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HPCA
2012
IEEE
13 years 8 months ago
2012
IEEE
Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond...
149
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HPCA
2012
IEEE
13 years 8 months ago
2012
IEEE
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
114
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ICS
2003
Tsinghua U.
15 years 5 months ago
2003
Tsinghua U.
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...