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114
Voted
HPCA
2005
IEEE
16 years 2 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
110
Voted
HPCA
2001
IEEE
16 years 2 months ago
2001
IEEE
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
114
Voted
HPCA
2001
IEEE
16 years 2 months ago
2001
IEEE
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point...
112
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ICS
2010
Tsinghua U.
15 years 11 months ago
2010
Tsinghua U.
We introduce the notion of "non-malleable codes" which relaxes the notion of error-correction and errordetection. Informally, a code is non-malleable if the message cont...
99
Voted
SPAA
2009
ACM
15 years 11 months ago
2009
ACM
In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is...