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ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
14 years 11 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
118
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FMSD
2007
110views more  FMSD 2007»
14 years 11 months ago
Exploiting interleaving semantics in symbolic state-space generation
Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, ...
Gianfranco Ciardo, Gerald Lüttgen, Andrew S. ...
113
Voted
CACM
2005
126views more  CACM 2005»
14 years 11 months ago
Extrovert gadgets
This paper presents a set of architectures for the composition of ubiquitous computing applications. It describes research that is being carried out in "extrovert-Gadgets&quo...
Achilles Kameas, Irene Mavrommati
SIGSOFT
2008
ACM
16 years 10 days ago
Empirical evidence of the benefits of workspace awareness in software configuration management
In this paper, we present results from our empirical evaluations of a workspace awareness tool that we designed and implemented to augment the functionality of software configurat...
Anita Sarma, David F. Redmiles, André van d...
CASES
2009
ACM
15 years 6 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...