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» Implementing Image Applications on FPGAs
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ICIP
1999
IEEE
16 years 6 months ago
Architecture of Embedded Video Processing in a Multimedia Chip-Set
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
Egbert G. T. Jaspers, Peter H. N. de With
ICIP
2009
IEEE
16 years 6 months ago
Mapping Motion Vectors For A Wyner-ziv Video Transcoder
Wyner-Ziv (WZ) coding of video utilizes simple encoders and highly complex decoders. A transcoder from a WZ codec to a traditional codec can potentially increase the range of appl...
MICCAI
2006
Springer
16 years 5 months ago
Towards Optimization of Probe Placement for Radio-Frequency Ablation
We present a model for the optimal placement of mono- and bipolar probes in radio-frequency (RF) ablation. The model is based on a numerical computation of the probe's electri...
Inga Altrogge, Tim Kröger, Tobias Preusser, C...
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
15 years 10 months ago
Convergent micro-pipelines: a versatile operator for mixed asynchronous-synchronous computations
Abstract— Micro-pipelines are linear (1-D) structures for asynchronous communications. In retinotopic VLSI vision chips, communicating over 2-D image regions is a key to efficie...
Valentin Gies, Thierry M. Bernard, Alain Mé...
ERSA
2009
131views Hardware» more  ERSA 2009»
15 years 2 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...