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CSREAESA
2009
15 years 23 days ago
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
Bradley F. Dutton, Charles E. Stroud
ISCC
2009
IEEE
151views Communications» more  ISCC 2009»
15 years 6 months ago
Hardware implementation of session initiation protocol servers and clients
—This paper presents a reconfigurable architecture for the session initiation protocol (SIP). SIP is a protocol used primarily to establish point-to-point sessions between users...
Raymond Peterkin, Mohamed Abou-Gabal, Fadi El-Hass...

Lecture Notes
1005views
16 years 12 months ago
Lectures on reconfigurable computing
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
Sherief Reda
FCCM
2004
IEEE
87views VLSI» more  FCCM 2004»
15 years 3 months ago
A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation
General purpose computing architectures are being called on to work on a more diverse application mix every day. This has been fueled by the need for reduced time to market and ec...
David Wentzlaff, Anant Agarwal
TVLSI
2008
149views more  TVLSI 2008»
14 years 11 months ago
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs
With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpo...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...