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» Implementing LDPC Decoding on Network-on-Chip
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118
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ICC
2007
IEEE
192views Communications» more  ICC 2007»
15 years 9 months ago
Informed Dynamic Scheduling for Belief-Propagation Decoding of LDPC Codes
— Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation, or message-passing, algorithm over the factor graph of the code. The tradi...
Andres I. Vila Casado, Miguel Griot, Richard D. We...
151
Voted
ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
15 years 8 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
111
Voted
ICC
2007
IEEE
124views Communications» more  ICC 2007»
15 years 9 months ago
Quantization Effects in Low-Density Parity-Check Decoders
−A class of combinatorial structures, called absorbing sets, strongly influences the performance of low-density paritycheck (LDPC) decoders. In particular, the quantization schem...
Zhengya Zhang, Lara Dolecek, Martin J. Wainwright,...
120
Voted
GLOBECOM
2008
IEEE
15 years 9 months ago
Lowering LDPC Error Floors by Postprocessing
−A class of combinatorial structures, called absorbing sets, strongly influences the performance of low-density paritycheck (LDPC) decoders at low error rates. Past experiments h...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...
112
Voted
ICASSP
2011
IEEE
14 years 6 months ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...