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IPPS
1995
IEEE
15 years 8 months ago
The RACE network architecture
The RACE R parallel computer system provides a highperformance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE ...
Bradley C. Kuszmaul
ICPP
2009
IEEE
15 years 2 months ago
Employing Transactional Memory and Helper Threads to Speedup Dijkstra's Algorithm
In this paper we work on the parallelization of the inherently serial Dijkstra's algorithm on modern multicore platforms. Dijkstra's algorithm is a greedy algorithm that ...
Konstantinos Nikas, Nikos Anastopoulos, Georgios I...
ASPLOS
2010
ACM
15 years 11 months ago
ParaLog: enabling and accelerating online parallel monitoring of multithreaded applications
Instruction-grain lifeguards monitor the events of a running application at the level of individual instructions in order to identify and help mitigate application bugs and securi...
Evangelos Vlachos, Michelle L. Goodstein, Michael ...
CGO
2008
IEEE
15 years 11 months ago
Spice: speculative parallel iteration chunk execution
The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level paralleli...
Easwaran Raman, Neil Vachharajani, Ram Rangan, Dav...
ICSM
2007
IEEE
15 years 11 months ago
Evaluation of Semantic Interference Detection in Parallel Changes: an Exploratory Experiment
Parallel developments are becoming increasingly prevalent in the building and evolution of large-scale software systems. Our previous studies of a large industrial project showed ...
Danhua Shao, Sarfraz Khurshid, Dewayne E. Perry