5562 search results - page 850 / 1113 » Implementing Parallel Cell-DEVS |
160
click to vote
PVLDB
2010
14 years 11 months ago
2010
The ever-increasing number of intrusions in public and commercial networks has created the need for high-speed archival solutions that continuously store streaming network data to...
153
click to vote
SIAMSC
2010
14 years 11 months ago
2010
In this paper we present HUND, a hypergraph-based unsymmetric nested dissection ordering algorithm for reducing the fill-in incurred during Gaussian elimination. HUND has several i...
156
click to vote
TCAD
2010
14 years 11 months ago
2010
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
206
click to vote
TVLSI
2010
14 years 11 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
295
Voted
GLVLSI
2011
IEEE
14 years 8 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...