Sciweavers

5562 search results - page 910 / 1113
» Implementing Parallel Cell-DEVS
Sort
View
DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
15 years 10 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
FMICS
2007
Springer
15 years 10 months ago
An Approach to Formalization and Analysis of Message Passing Libraries
Message passing using libraries implementing the Message Passing Interface (MPI) standard is the dominant communication mechanism in high performance computing (HPC) applications. ...
Robert Palmer, Michael Delisi, Ganesh Gopalakrishn...
ICS
2007
Tsinghua U.
15 years 10 months ago
Adaptive Strassen's matrix multiplication
Strassen’s matrix multiplication (MM) has benefits with respect to any (highly tuned) implementations of MM because Strassen’s reduces the total number of operations. Strasse...
Paolo D'Alberto, Alexandru Nicolau
WAIM
2007
Springer
15 years 10 months ago
A New DBMS Architecture for DB-IR Integration
Nowadays, as there is an increasing need to integrate the DBMS (for structured data) with Information Retrieval (IR) features (for unstructured data), DB-IR integration becomes one...
Kyu-Young Whang
149
Voted
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
15 years 10 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...