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» Implementing Performance Competitive Logical Recovery
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TIME
2005
IEEE
13 years 12 months ago
A Trace Semantics for Positive Core XPath
— We provide a novel trace semantics for positive core XPath that exposes all intermediate nodes visited by the query engine. This enables a detailed analysis of all information ...
Pieter H. Hartel
EURODAC
1994
IEEE
122views VHDL» more  EURODAC 1994»
13 years 10 months ago
Compiled-code-based simulation with timing verification
Due to the complexity of today's systems, prototyping by simulation must be based on simulation-engine-like performance. It is proved by implementations that compiler-driven ...
Winfried Hahn, Andreas Hagerer, C. Herrmann
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
13 years 11 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
WSC
2004
13 years 7 months ago
Controlling Over-Optimism in Time-Warp Via CPU-Based Flow Control
In standard optimistic parallel event simulation, no restriction exists on the maximum lag in simulation time between the fastest and slowest logical processes (LPs). Overoptimist...
Vinay Sachdev, Maria Hybinette, Eileen Kraemer
DAC
2006
ACM
14 years 7 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang