1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the ...
A Gm- C architecture for a quadrature, sinusoidal os- ± Vref cillator with instantaneous, phase-preserving, linear frequency control Peak detector and independent, static amplitud...
An architecture and implementation of a high performance Gaussian random number generator (GRNG) is described. The GRNG uses the Ziggurat algorithm which divides the area under th...
Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee,...
With-loops are versatile array comprehensions used in the functional array language SaC to implement universally applicable array operations. We describe the fusion of with-loops a...
A machine cycle CPU simulator is developed on the Squeak environment for educational use. The developed simulator is able to show hardware behavior in CPU at each system clock. An...