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ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
14 years 12 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
CODES
2009
IEEE
15 years 6 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
KBSE
2009
IEEE
15 years 6 months ago
Static Validation of C Preprocessor Macros
—The widely used C preprocessor (CPP) is generally considered a source of difficulty for understanding and maintaining C/C++ programs. The main reason for this difficulty is CP...
Andreas Saebjoernsen, Lingxiao Jiang, Daniel J. Qu...
MEMOCODE
2003
IEEE
15 years 5 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
BMCBI
2005
124views more  BMCBI 2005»
14 years 11 months ago
Tools enabling the elucidation of molecular pathways active in human disease: Application to Hepatitis C virus infection
Background: The extraction of biological knowledge from genome-scale data sets requires its analysis in the context of additional biological information. The importance of integra...
David J. Reiss, Iliana Avila-Campillo, Vesteinn Th...