857 search results - page 105 / 172 » Implementing a STARI chip |
FPT
2005
IEEE
15 years 3 months ago
2005
IEEE
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
ICRA
2005
IEEE
15 years 3 months ago
2005
IEEE
– We describe in detail the behavior of an inhibitory Central Pattern Generator (CPG) network for robot control. A four-neuron, mutual inhibitory network forms the basic coordina...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
—Efficient routing schemes are essential if Network on Chip (NoC) architectures are to be used for implementing multi-core systems for real-time multi-media applications. These s...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
Abstract— Micro-pipelines are linear (1-D) structures for asynchronous communications. In retinotopic VLSI vision chips, communicating over 2-D image regions is a key to efficie...
ISPASS
2005
IEEE
15 years 3 months ago
2005
IEEE
We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use— instrument...