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» Implementing a STARI chip
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ATS
2001
IEEE
137views Hardware» more  ATS 2001»
15 years 1 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
15 years 1 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
DSN
2008
IEEE
14 years 11 months ago
Detouring: Translating software to circumvent hard faults in simple cores
CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Wherea...
Albert Meixner, Daniel J. Sorin
JFPLC
2004
14 years 11 months ago
Explications pour comprendre la trace d'un solveur de contraintes sur domaines finis
ABSTRACT. Some works in progress on finite domain constraint solvers concern the implementation of a XML trace of the computation according to the OADymPPaC DTD (for example in GNU...
Gérard Ferrand, Willy Lesaint, Alexandre Te...
NIPS
2000
14 years 11 months ago
Homeostasis in a Silicon Integrate and Fire Neuron
In this work, we explore homeostasis in a silicon integrate-and-fire neuron. The neuron adapts its firing rate over long time periods on the order of seconds or minutes so that it...
Shih-Chii Liu, Bradley A. Minch