857 search results - page 111 / 172 » Implementing a STARI chip |
ETS
2010
IEEE
14 years 11 months ago
2010
IEEE
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...
INFORMATICALT
2006
14 years 9 months ago
2006
We know the necessity for information security becomes more widespread in these days, especially for hardware-based implementations such as smart cards chips for wireless applicati...
PPL
2006
14 years 9 months ago
2006
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
GLOBECOM
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract-- This work deals with devising a secure, powerefficient, beam-steerable and on-chip transmission system for wireless sensor networks. A passively controllable smart (PCS)...
NOCS
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...