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» Implementing a STARI chip
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PLDI
2011
ACM
14 years 18 days ago
Caisson: a hardware description language for secure information flow
Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system’s roo...
Xun Li 0001, Mohit Tiwari, Jason Oberg, Vineeth Ka...
ICDE
2009
IEEE
171views Database» more  ICDE 2009»
15 years 4 months ago
CoTS: A Scalable Framework for Parallelizing Frequency Counting over Data Streams
Applications involving analysis of data streams have gained significant popularity and importance. Frequency counting, frequent elements and top-k queries form a class of operato...
Sudipto Das, Shyam Antony, Divyakant Agrawal, Amr ...
NOCS
2007
IEEE
15 years 4 months ago
Transaction-Based Communication-Centric Debug
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...
Kees Goossens, Bart Vermeulen, Remco van Steeden, ...
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 2 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
ASAP
2010
IEEE
171views Hardware» more  ASAP 2010»
14 years 10 months ago
General-purpose FPGA platform for efficient encryption and hashing
Many applications require protection of secret or sensitive information, from sensor nodes and embedded applications to large distributed systems. The confidentiality of data can b...
Jakub Szefer, Yu-Yuan Chen, Ruby B. Lee