Sciweavers

857 search results - page 151 / 172
» Implementing a STARI chip
Sort
View
IPPS
2006
IEEE
15 years 10 months ago
Parallel genetic algorithm for SPICE model parameter extraction
Models of simulation program with integrated circuit emphasis (SPICE) are currently playing a central role in the connection between circuit design and chip fabrication communitie...
Yiming Li, Yen-Yu Cho
SAMOS
2004
Springer
15 years 9 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
CASES
2005
ACM
15 years 6 months ago
SECA: security-enhanced communication architecture
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Sri...
NIPS
2007
15 years 5 months ago
An in-silico Neural Model of Dynamic Routing through Neuronal Coherence
We describe a neurobiologically plausible model to implement dynamic routing using the concept of neuronal communication through neuronal coherence. The model has a three-tier arc...
Devarajan Sridharan, Brian Percival, John V. Arthu...
BMCBI
2010
96views more  BMCBI 2010»
15 years 4 months ago
ChIPpeakAnno: a Bioconductor package to annotate ChIP-seq and ChIP-chip data
Background: Chromatin immunoprecipitation (ChIP) followed by high-throughput sequencing (ChIP-seq) or ChIP followed by genome tiling array analysis (ChIP-chip) have become standar...
Lihua J. Zhu, Claude Gazin, Nathan D. Lawson, Herv...