857 search results - page 157 / 172 » Implementing a STARI chip |
102
Voted
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new na...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
101
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KDD
2008
ACM
15 years 10 months ago
2008
ACM
Multi-core processors with ever increasing number of cores per chip are becoming prevalent in modern parallel computing. Our goal is to make use of the multi-core as well as multi...
101
click to vote
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...