Sciweavers

857 search results - page 45 / 172
» Implementing a STARI chip
Sort
View
ICCSA
2007
Springer
15 years 1 months ago
A Novel Congestion Control Scheme for Elastic Flows in Network-on-Chip Based on Sum-Rate Optimization
Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated busses in order to achieve modularity and high performance in the future System-on-Chi...
Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khon...
DAC
2005
ACM
14 years 11 months ago
Keeping hot chips cool
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
JOC
2011
104views more  JOC 2011»
14 years 18 days ago
On the Security of Oscillator-Based Random Number Generators
Physical random number generators (a.k.a. TRNGs) appear to be critical components of many cryptographic systems. Yet, such building blocks are still too seldom provided with a form...
Mathieu Baudet, David Lubicz, Julien Micolod, Andr...
IPPS
2002
IEEE
15 years 2 months ago
Multipartite Tables in JBits for the Evaluation of Functions on FPGAs
This paper presents the implementation, on Virtex FPGAs, of a core generator for arbitrary numeric functions in fixed-point format. The cores use the state-of-theart multipartite...
Jérémie Detrey, Florent de Dinechin
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
15 years 6 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras