857 search results - page 46 / 172 » Implementing a STARI chip |
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
ITNG
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
ITNG
2007
IEEE
15 years 4 months ago
2007
IEEE
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...