857 search results - page 51 / 172 » Implementing a STARI chip |
ASYNC
2000
IEEE
15 years 2 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
ERSA
2006
14 years 11 months ago
2006
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
CASES
2006
ACM
15 years 3 months ago
2006
ACM
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
CISIS
2008
IEEE
15 years 4 months ago
2008
IEEE
As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifte...
118
click to vote
VLSID
2001
IEEE
15 years 10 months ago
2001
IEEE
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...