857 search results - page 54 / 172 » Implementing a STARI chip |
ISCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
108
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TVLSI
2008
14 years 9 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
CF
2009
ACM
15 years 4 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
103
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DSN
2007
IEEE
15 years 4 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...