Sciweavers

857 search results - page 58 / 172
» Implementing a STARI chip
Sort
View
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
15 years 7 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
142
Voted
BMCBI
2010
154views more  BMCBI 2010»
15 years 4 months ago
Motif Enrichment Analysis: a unified framework and an evaluation on ChIP data
Background: A major goal of molecular biology is determining the mechanisms that control the transcription of genes. Motif Enrichment Analysis (MEA) seeks to determine which DNA-b...
Robert C. McLeay, Timothy L. Bailey
TCAD
2008
114views more  TCAD 2008»
15 years 4 months ago
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...
GCB
2009
Springer
481views Biometrics» more  GCB 2009»
15 years 10 months ago
CUDA-based Multi-core Implementation of MDS-based Bioinformatics Algorithms
: Solving problems in bioinformatics often needs extensive computational power. Current trends in processor architecture, especially massive multi-core processors for graphic cards...
Thilo Fester, Falk Schreiber, Marc Strickert
157
Voted
IPPS
2006
IEEE
15 years 10 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...