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» Implementing a STARI chip
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NOCS
2007
IEEE
15 years 4 months ago
NoC Design and Implementation in 65nm Technology
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
Antonio Pullini, Federico Angiolini, Paolo Meloni,...
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
15 years 3 months ago
Time Domain Multiplexed TAM: Implementation and Comparison
One of the difficult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are no...
Zahra Sadat Ebadi, André Ivanov
VTC
2007
IEEE
109views Communications» more  VTC 2007»
15 years 4 months ago
A Reliability-Aware LDPC Code Decoding Algorithm
— With the continuing downscaling of microelectronic technology, chip reliability becomes a great threat to the design of future complex microelectronic systems. Hence increasing...
Matthias Alles, Torben Brack, Norbert Wehn
INTEGRATION
2008
183views more  INTEGRATION 2008»
14 years 9 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
BMCBI
2010
87views more  BMCBI 2010»
14 years 10 months ago
poolMC: Smart pooling of mRNA samples in microarray experiments
Background: Typically, pooling of mRNA samples in microarray experiments implies mixing mRNA from several biological-replicate samples before hybridization onto a microarray chip....
Raghunandan M. Kainkaryam, Angela Bruex, Anna C. G...