857 search results - page 61 / 172 » Implementing a STARI chip |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Chip reliability becomes a great threat to the design of future microelectronic systems with the continuation of the progressive downscaling of CMOS technologies. Hence increasing...
ISCAS
2008
IEEE
15 years 4 months ago
2008
IEEE
— In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits fr...
ICMCS
2006
IEEE
15 years 3 months ago
2006
IEEE
We present a low-power architectural MPEG-4 part-10 AVC/H.264 video and MPEG-4 BSAC audio decoder chip capable of delivering high-quality and high-compression in wireless multimed...
IWANN
1999
Springer
15 years 2 months ago
1999
Springer
Recently, a real-time clustering microchip based on the ART1 algorithm has been reported. That chip was able to classify 100-bit input patterns into up to 18 categories. However, i...
ICCD
1993
IEEE
15 years 1 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...