857 search results - page 62 / 172 » Implementing a STARI chip |
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric...
INFOCOM
2010
IEEE
14 years 7 months ago
2010
IEEE
It is becoming apparent that the next generation IP route lookup architecture needs to achieve speeds of 100Gbps and beyond while supporting both IPv4 and IPv6 with fast real-time ...
BMCBI
2010
14 years 4 months ago
2010
Background: The brightness of the probe spots on expression microarrays intends to measure the abundance of specific mRNA targets. Probes with runs of at least three guanines (G) ...
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
We present a low-power analog circuit for implementing a model of a leaky integrate and fire neuron. Next to being optimized for low-power consumption, the proposed circuit inclu...
ISPASS
2009
IEEE
15 years 4 months ago
2009
IEEE
This paper analyzes the performance of the TRIPS prototype chip’s block predictor. The prototype is the first implementation of the block-atomic TRIPS architecture, wherein the...